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<A NAME="chip_types"></A>
<H2>Serial chip types</H2>

<UL>
<LI>8250 and 8250B have no scratch register
<LI>8250A and 16450 have the scratch register but no FIFO
<LI>16550 has a FIFO but it doesn't work
<LI>16550A has a 16-byte FIFO
<LI>16650 has a 32-byte FIFO, on-chip flow control, and can run up
to 460800 baud (4x normal)
<LI>16750 has a 64-byte FIFO, on-chip flow control, and can run up
to 921600 baud (8x normal). This chip is NOT pin-compatible
with the others.
</UL>

<B>8250-series chips (including 8250A) have these problems</B>:


<UL>
<LI>They can not keep up with PC/AT I/O speed, so delays must
  be inserted between successive I/O instructions
<LI>They transmit bad data when configured for 5 data bits
  with 1.5 stop bits
<LI>They can occasionally drop received characters without
  posting a receive overrun error.  This results in
  undetected data loss.
<LI>They can transmit a single random character at power on
</UL>

There is <B>no way to distinguish between 8250A and 16450</B> in software.

<A NAME="registers"></A>
<H2>Serial chip registers</H2>

<!-- Warning: must use closing tags for TABLE, TH, TR, and TD
because of nested tables -->

<TABLE BORDER><TR>
 <TH></TH>
 <TH COLSPAN="2">Read</TH>
 <TH COLSPAN="2">Write</TH>
</TR><TR>
 <TH>Register number</TH>
 <TH>DLAB=0</TH>
 <TH>DLAB=1</TH>

 <TH>DLAB=0</TH>
 <TH>DLAB=1</TH>
 <TH>Register name(s)</TH>
 <TH>Notes</TH>
</TR><TR>
 <TD ALIGN="CENTER">0</TD>
 <TD ALIGN="CENTER">RBR</TD>

 <TD ALIGN="CENTER">DLL</TD>
 <TD ALIGN="CENTER">THR</TD>
 <TD ALIGN="CENTER">DLL</TD>
 <TD>Receiver Buffer Register<BR>
	Divisor Latch LSB<BR>
        Transmitter Holding Register</TD>

</TR><TR>
 <TD ALIGN="CENTER">1</TD>
 <TD ALIGN="CENTER">IER</TD>
 <TD ALIGN="CENTER">DLM</TD>
 <TD ALIGN="CENTER">IER</TD>
 <TD ALIGN="CENTER">DLM</TD>
 <TD>Interrupt Enable Register<BR>

        Divisor Latch MSB</TD>
</TR><TR>
 <TD ALIGN="CENTER" ROWSPAN="3">2</TD>
 <TD ALIGN="CENTER" COLSPAN="2">IIR</TD>
 <TD COLSPAN="2"></TD>
 <TD>Interrupt ID Register</TD>
 <TD>8250-16450 chips (no FIFO)</TD>

</TR><TR>
 <TD ALIGN="CENTER" COLSPAN="2">IIR</TD>
 <TD ALIGN="CENTER" COLSPAN="2">FCR</TD>
 <TD>FIFO Control Register</TD>
 <TD>16550-series chips</TD>
</TR><TR>
 <TD ALIGN="CENTER" COLSPAN="2">IIR</TD>

 <TD ALIGN="CENTER">FCR</TD>
 <TD ALIGN="CENTER">EFR</TD>
 <TD>Enhanced FIFO control Register</TD>
 <TD>16650+ chips</TD>
</TR><TR>
 <TD ALIGN="CENTER">3</TD>
 <TD ALIGN="CENTER" COLSPAN="4">LCR</TD>

 <TD>Line Control Register</TD>
</TR><TR>
 <TD ALIGN="CENTER">4</TD>
 <TD ALIGN="CENTER" COLSPAN="4">MCR</TD>
 <TD>Modem Control Register</TD>
</TR><TR>
 <TD ALIGN="CENTER">5</TD>

 <TD ALIGN="CENTER" COLSPAN="4">LSR</TD>
 <TD>Line Status Register</TD>
</TR><TR>
 <TD ALIGN="CENTER">6</TD>
 <TD ALIGN="CENTER" COLSPAN="4">MSR</TD>
 <TD>Modem Status Register</TD>
</TR><TR>

 <TD ALIGN="CENTER">7</TD>
 <TD ALIGN="CENTER" COLSPAN="4">SCR</TD>
 <TD>SCRatch Register</TD>
 <TD>8250A and 16450+ chips</TD>
</TR></TABLE>

DLAB is bit b7 in the Line Control Register (see below).
<P>
The bit rate is normally 115200 divided by the 16-bit Divisor Latch value.
 According to one 16550A spec sheet, 'Using a value of 0 is not recommended.'

<P>
Reading RBR (register 0) clears the Receive Data and FIFO Timeout Interrupts.
<P>
Writing THR (register 0) clears the Transmit Holding Register Empty Interrupt.
 If you have nothing more to transmit, reading the Interrupt ID Register (IIR)
 will also clear this interrupt.

<H3>Register 1: Interrupt Enable Register (IER)</H3>

<TABLE BORDER><TR>
 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>

</TR><TR>
 <TD>0</TD><TD>0</TD><TD>0</TD><TD>0</TD><TD>EDSI</TD><TD>ELSI</TD><TD>ETBEI</TD><TD>ERBFI</TD>
</TR></TABLE>

<TABLE><TR>
 <TD>b3</TD>

 <TD>EDSI</TD>
 <TD>Enable moDem Status Interrupt (DCD, RI, DSR, CTS, etc.)</TD>
</TR><TR>
 <TD>b2</TD>
 <TD>ELSI</TD>
 <TD>Enable Line Status Interrupt (BI, FE, PE, or OE)</TD>
</TR><TR>

 <TD>b1</TD>
 <TD>ETBEI</TD>
 <TD>Enable Transmitter Buffer Empty Interrupt (when THR is empty).</TD>
</TR><TR>
 <TD>b0</TD>
 <TD>ERBFI</TD>
 <TD>Enable Receiver Buffer Full Interrupt. In FIFO mode, this bit
 also enables the FIFO timeout interrupt.</TD>

</TR></TABLE>

<P>
The receive FIFO timeout occurs automatically, when
<UL>
<LI>there is data in the receive FIFO, but
<LI>not enough data in the FIFO to trigger a normal Receiver Buffer Full interrupt, and
<LI>incoming data stops for a period of 4 character times or longer.
</UL>

<H3>Register 2: Interrupt ID Register (IIR; read-only)</H3>

<TABLE BORDER><TR>
 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>

</TR><TR>
 <TD>fe1</TD><TD>fe0</TD><TD>0</TD><TD>0</TD><TD>id2</TD><TD>id1</TD><TD>id0</TD><TD>nint</TD>
</TR></TABLE>

<TABLE><TR>
 <TD VALIGN="TOP">b7-b6</TD>

 <TD VALIGN="TOP">fe1-fe0</TD>
 <TD>When FIFOs are enabled, these bits identify the serial chip:
	<TABLE><TR>
	 <TH>fe1</TH>   <TH>fe0</TH>    <TH>chip</TH>
	</TR><TR>
	 <TD>0</TD>     <TD>0</TD>      <TD>8250/16450 (no FIFO)</TD>

	</TR><TR>
	 <TD>0</TD>     <TD>1</TD>      <TD>UNKNOWN</TD>
	</TR><TR>
         <TD>1</TD>     <TD>0</TD>      <TD>16550 (defective FIFO)</TD>

	</TR><TR>
         <TD>1</TD>     <TD>1</TD>      <TD>16550A+</TD>
	</TR></TABLE></TD>
</TR><TR>
 <TD VALIGN="TOP">b3-b1</TD>
 <TD VALIGN="TOP">id2-id0</TD>

 <TD>These bits identify the interrupt source:
	<TABLE><TR>
	 <TH>id2</TH><TH>id1</TH><TH>id0</TH><TH>Priority</TH><TH>Interrupt source</TH>
	</TR><TR>
	 <TD>0</TD><TD>0</TD><TD>0</TD><TD>4th</TD><TD>Modem status changed (DCD, RI, DSR, CTS, etc.)</TD>

	</TR><TR>
	 <TD>0</TD><TD>0</TD><TD>1</TD><TD>3rd</TD><TD>THR or transmit FIFO empty</TD>
	</TR><TR>
	 <TD>0</TD><TD>1</TD><TD>0</TD><TD>2nd</TD><TD>RBR or receive FIFO full</TD>

	</TR><TR>
	 <TD>0</TD><TD>1</TD><TD>1</TD><TD>1st</TD><TD>Line status changed (BI, FE, PE, or OE)</TD>
	</TR><TR>
	 <TD>1</TD><TD>0</TD><TD>0</TD><TD>-</TD><TD>-</TD>

	</TR><TR>
	 <TD>1</TD><TD>0</TD><TD>1</TD><TD>-</TD><TD>-</TD>
	</TR><TR>
	 <TD>1</TD><TD>1</TD><TD>0</TD><TD>2nd</TD><TD>(16550+ only) Receive FIFO timeout</TD>

	</TR><TR>
	 <TD>1</TD><TD>1</TD><TD>1</TD><TD>-</TD><TD>-</TD>
	</TR></TABLE></TD>
</TR><TR>
 <TD VALIGN="TOP">b0</TD>
 <TD VALIGN="TOP">nint</TD>

 <TD>This bit =0 if the chip is currently signalling an interrupt.
     <B>This bit is ACTIVE LOW.</B></TD>
</TR></TABLE>


<H3>Register 2: FIFO Control Register (FCR; write-only; 16550+)</H3>

<TABLE BORDER><TR>
 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>

</TR><TR>
 <TD>trig1</TD><TD>trig0</TD><TD>0</TD><TD>0</TD><TD>dma</TD><TD>rtf</TD><TD>rrf</TD><TD>fe</TD>
</TR></TABLE>

<TABLE><TR>
 <TD VALIGN="TOP">b7-b6</TD>

 <TD VALIGN="TOP">trig1-trig0</TD>
 <TD>Receiver FIFO interrupt trigger level:
	<TABLE><TR>
	 <TH COLSPAN="2"></TH>  <TH COLSPAN="3">Receive FIFO size (bytes)</TH>
	</TR><TR>
	 <TH>trig1</TH><TH>trig0</TH><TH>16550</TH><TH>16650</TH><TH>16750</TH>

	</TR><TR>
	 <TD>0</TD><TD>0</TD><TD>1</TD><TD>8</TD><TD>1</TD>
	</TR><TR>
	 <TD>0</TD><TD>1</TD><TD>4</TD><TD>16</TD><TD>16</TD>

	</TR><TR>
	 <TD>1</TD><TD>0</TD><TD>8</TD><TD>24</TD><TD>32</TD>
	</TR><TR>
	 <TD>1</TD><TD>1</TD><TD>14</TD><TD>28</TD><TD>56</TD>

	</TR></TABLE></TD>
</TR><TR>
 <TD>b3</TD>
 <TD>dma</TD>
 <TD>?</TD>
</TR><TR>
 <TD>b2</TD>
 <TD>rtf</TD>

 <TD>Reset Transmit FIFO. The transmitter shift register is not affected.
     This bit is self-clearing.</TD>
</TR><TR>
 <TD>b1</TD>
 <TD>rrf</TD>
 <TD>Reset Receive FIFO. The receiver shift register is not affected.
     This bit is self-clearing.</TD>
</TR><TR>
 <TD VALIGN="TOP">b0</TD>

 <TD VALIGN="TOP">fe</TD>
 <TD>Enable FIFOs. Setting or clearing this bit clears the FIFOs.
     <B>b7-b1 will not be written unless b0=1</B></TD>
</TR></TABLE>

<H3>Register 2: Enhanced FIFO control Register (EFR; write-only; 16650+)</H3>

?

<H3>Register 3: Line Control Register (LCR)</H3>

<TABLE BORDER><TR>

 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>
</TR><TR>
 <TD>DLAB</TD><TD>BREAK</TD><TD>STICK</TD><TD>EPS</TD><TD>PEN</TD><TD>STB</TD><TD>WLS1</TD><TD>WLS0</TD>

</TR></TABLE>

<TABLE><TR>
 <TD>b7</TD>
 <TD>DLAB</TD>
 <TD>Divisor Latch Access Bit. Enables access to bit rate divisor latch
     in registers 0 and 1</TD>
</TR><TR>
 <TD>b6</TD>
 <TD>BREAK</TD>

 <TD>Setting this bit causes the serial output to send a continuous 'space'
     condition</TD>
</TR><TR>
 <TD>b5</TD>
 <TD>STICK</TD>
 <TD>Stick parity</TD>
</TR><TR>
 <TD>b4</TD>

 <TD>EPS</TD>
 <TD>Even Parity Select</TD>
</TR><TR>
 <TD VALIGN="TOP">b3</TD>
 <TD VALIGN="TOP">PEN</TD>
 <TD>Parity ENable:
	<TABLE><TR>
         <TH>STICK</TH>  <TH>EPS</TH>  <TH>PEN</TH>  <TH>Parity</TH>

	</TR><TR>
         <TD>-</TD>  <TD>-</TD>  <TD>0</TD>  <TD>None</TD>
	</TR><TR>
         <TD>0</TD>  <TD>0</TD>  <TD>1</TD>  <TD>Odd</TD>

	</TR><TR>
         <TD>0</TD>  <TD>1</TD>  <TD>1</TD>  <TD>Even</TD>
	</TR><TR>
         <TD>1</TD>  <TD>0</TD>  <TD>1</TD>  <TD>Stuck-at-1 (mark parity)</TD>

	</TR><TR>
         <TD>1</TD>  <TD>1</TD>  <TD>1</TD>  <TD>Stuck-at-0 (space parity)</TD>
        </TR></TABLE></TD>
</TR><TR>
 <TD>b2</TD>

 <TD>STB</TD>
 <TD>number of STop Bits</TD>
</TR><TR>
 <TD VALIGN="TOP">b1-b0</TD>
 <TD VALIGN="TOP">WLS1-WLS0</TD>
 <TD>Word Length Select:
	<TABLE><TR>
	 <TH>STB</TH><TH>WLS1</TH><TH>WLS0</TH><TH>Data bits</TH><TH>Stop bits</TH>

	</TR><TR>
	 <TD>0</TD><TD>0</TD><TD>0</TD><TD>5</TD><TD>1</TD>
	</TR><TR>
	 <TD>0</TD><TD>0</TD><TD>1</TD><TD>6</TD><TD>1</TD>

	</TR><TR>
	 <TD>0</TD><TD>1</TD><TD>0</TD><TD>7</TD><TD>1</TD>
	</TR><TR>
	 <TD>0</TD><TD>1</TD><TD>1</TD><TD>8</TD><TD>1</TD>

	</TR><TR>
	 <TD>1</TD><TD>0</TD><TD>0</TD><TD>5</TD><TD>1.5</TD>
	</TR><TR>
	 <TD>1</TD><TD>0</TD><TD>1</TD><TD>6</TD><TD>2</TD>

	</TR><TR>
	 <TD>1</TD><TD>1</TD><TD>0</TD><TD>7</TD><TD>2</TD>
	</TR><TR>
	 <TD>1</TD><TD>1</TD><TD>1</TD><TD>8</TD><TD>2</TD>

	</TR></TABLE></TD>
</TR></TABLE>
<I>Parity</I> is an optional extra bit sent with each data byte. It lets
 the receiver detect single-bit transmission errors.

<H3>Register 4: Modem Control Register (MCR)</H3>

<TABLE BORDER><TR>
 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>

</TR><TR>
 <TD>clkx4</TD><TD>iren</TD><TD>it/fc</TD><TD>LOOP</TD><TD>Out2</TD><TD>Out1</TD><TD>RTS</TD><TD>DTR</TD>
</TR></TABLE>

<TABLE><TR>
 <TD VALIGN="TOP">b7</TD>

 <TD VALIGN="TOP">clkx4</TD>
 <TD>[16750 only] Enables x4 clock (?)</TD>
</TR><TR>
 <TD VALIGN="TOP">b6</TD>
 <TD VALIGN="TOP">iren</TD>
 <TD>[16650 only] IR enable (?)</TD>
</TR><TR>

 <TD VALIGN="TOP">b5</TD>
 <TD VALIGN="TOP">it/fc</TD>
 <TD>[16650 only] Interrupt type select (?)<BR>
     [16750 only] Flow control enable (?)</TD>
</TR><TR>
 <TD VALIGN="TOP">b4</TD>
 <TD VALIGN="TOP">LOOP</TD>

 <TD>Loopback. Serial chip signals are disconnected from the outside world
     and internally looped back as shown here:
     <BLOCKQUOTE>
	DTR  ---> DSR<BR>
	RTS  ---> CTS<BR>
	OUT1 ---> RI<BR>
	OUT2 ---> DCD<BR>
	Tx   ---> Rx
     </BLOCKQUOTE>

     <B>In some serial chips, loopback is not supported</B> at all.
     In other chips, the handshaking lines are looped back as shown,
     but there is no Tx --> Rx loopback.</TD>
</TR><TR>
 <TD VALIGN="TOP">b3</TD>
 <TD VALIGN="TOP">Out2</TD>
 <TD>User-defined output bit. <B>For most serial ports, this bit must be
 set to enable interrupts from the chip.</B></TD>
</TR><TR>

 <TD VALIGN="TOP">b2</TD>
 <TD VALIGN="TOP">Out1</TD>
 <TD>User-defined output bit.</TD>
</TR><TR>
 <TD VALIGN="TOP">b1</TD>
 <TD VALIGN="TOP">RTS</TD>
 <TD>Ready To Send handshaking output.</TD>

</TR><TR>
 <TD VALIGN="TOP">b0</TD>
 <TD VALIGN="TOP">DTR</TD>
 <TD>Data Terminal Ready handshaking output.</TD>
</TR></TABLE>

<H3>Register 5 (read-only): Line Status Register (LSR)</H3>

Reading this register clears the Line Status Interrupt.
<P>

<TABLE BORDER><TR>
 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>
</TR><TR>
 <TD>rfe</TD><TD>TEMT</TD><TD>THRE</TD><TD>BI</TD><TD>FE</TD><TD>PE</TD><TD>OE</TD><TD>DR</TD>

</TR></TABLE>

<TABLE><TR>
 <TD VALIGN="TOP">b7</TD>
 <TD VALIGN="TOP">rfe</TD>
 <TD>[16550+] Receive FIFO error. Indicates that at least one byte in the
     receive FIFO contains a parity error, framing error, or BREAK. If the
     FIFOs are disabled or the chip has no FIFOs, this bit =0</TD>
</TR><TR>
 <TD VALIGN="TOP">b6</TD>
 <TD VALIGN="TOP">TEMT</TD>

 <TD>Transmitter Empty. Indicates that the THR, FIFO, and transmit shift
     register are all empty. <B>This bit does not generate an interrupt</B>.
     If you want to use stick parity to transmit 9-bit values, you can't
     change the stick parity value until the transmitter is empty, so you
     must poll this bit. You must also disable the FIFOs to send 9-bit
     values.</TD>
</TR><TR>
 <TD VALIGN="TOP">b5</TD>
 <TD VALIGN="TOP">THRE</TD>
 <TD>Transmitter Holding Register Empty. Set when transmitter is ready
     to accept a new character.</TD>
</TR><TR>
 <TD VALIGN="TOP">b4</TD>

 <TD VALIGN="TOP">BI</TD>
 <TD>Break Indication. This bit is set if a BREAK is received. BREAK is
     a 'space' condition that lasts for at least ???</TD>
</TR><TR>
 <TD VALIGN="TOP">b3</TD>
 <TD VALIGN="TOP">FE</TD>
 <TD>Framing error (invalid stop bit) in received data.</TD>
</TR><TR>

 <TD VALIGN="TOP">b2</TD>
 <TD VALIGN="TOP">PE</TD>
 <TD>Parity error in received data.</TD>
</TR><TR>
 <TD VALIGN="TOP">b1</TD>
 <TD VALIGN="TOP">OE</TD>
 <TD>Overrun error. New data was received before the old data in the
     Receiver Buffer Fegister or FIFO was read.</TD>

</TR><TR>
 <TD VALIGN="TOP">b0</TD>
 <TD VALIGN="TOP">DR</TD>
 <TD>Data ready. This bit is set when a complete character has been
     received and transferred to the Receiver Buffer Register or FIFO.
	<P>
     The error bits are set when the associated byte is at the top of
     the FIFO.</TD>
</TR></TABLE>

<H3>Register 6: Modem Status Register (MSR)</H3>

Reading this register clears the Modem Status Interrupt.
<P>
<TABLE BORDER><TR>
 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>
</TR><TR>
 <TD>DCD</TD><TD>RI</TD><TD>DSR</TD><TD>CTS</TD><TD>DDCD</TD><TD>TERI</TD><TD>DDSR</TD><TD>DCTS</TD>

</TR></TABLE>

<TABLE><TR>
 <TD VALIGN="TOP">b7</TD>
 <TD VALIGN="TOP">DCD</TD>
 <TD>Data Carrier Detect handshaking input.</TD>
</TR><TR>
 <TD VALIGN="TOP">b6</TD>
 <TD VALIGN="TOP">RI</TD>

 <TD>Ring Indication handshaking input.</TD>
</TR><TR>
 <TD VALIGN="TOP">b5</TD>
 <TD VALIGN="TOP">DSR</TD>
 <TD>Data Set Ready handshaking input.</TD>
</TR><TR>
 <TD VALIGN="TOP">b4</TD>

 <TD VALIGN="TOP">CTS</TD>
 <TD>Clear To Send handshaking input.</TD>
</TR><TR>
 <TD VALIGN="TOP">b3</TD>
 <TD VALIGN="TOP">DDCD</TD>
 <TD>Delta DCD. Set if DCD line changed state.</TD>
</TR><TR>

 <TD VALIGN="TOP">b2</TD>
 <TD VALIGN="TOP">TERI</TD>
 <TD>Trailing Edge RI.</TD>
</TR><TR>
 <TD VALIGN="TOP">b1</TD>
 <TD VALIGN="TOP">DDSR</TD>
 <TD>Delta DSR. Set if DSR line changed state.</TD>

</TR><TR>
 <TD VALIGN="TOP">b0</TD>
 <TD VALIGN="TOP">DCTS</TD>
 <TD>Delta CTS. Set if CTS line changed state.</TD>
</TR></TABLE>

<H3>Register 7: Scratch Register (SCR)</H3>

<TABLE BORDER><TR>
 <TH>b7</TH><TH>b6</TH><TH>b5</TH><TH>b4</TH><TH>b3</TH><TH>b2</TH><TH>b1</TH><TH>b0</TH>

</TR><TR>
 <TD>-</TD><TD>-</TD><TD>-</TD><TD>-</TD><TD>-</TD><TD>-</TD><TD>-</TD><TD>-</TD>
</TR></TABLE>
<P>
You can store whatever you want in this register. It is not present,
 however, in 8250 and 8250B chips.

<A NAME="snippets"></A>
<H2>Code snippets</H2>

<A HREF="serial-3.html">Serial port demo/driver code</A>
<P>
<A HREF="pollout.html">Simple polled serial output</A> (good for debugging)

<A NAME="links"></A>
<H2>Links</H2>

Specs for National Semiconductor PC16550D serial chip:
 <A HREF="http://www.national.com/pf/PC/PC16550D.html">
 http://www.national.com/pf/PC/PC16550D.html</A>

<A NAME="todo"></A>
<H2>TO DO</H2>

<PRE>
- info on using DMA with serial chips (b3 in FCR)
- Enhanced FIFO control Register (EFR; 16650+ chips)
- clkx4, iren, it/fc bits in reg 4 (16650/16570 chips)
</PRE>

<A NAME="errors"></A>
<H2><A HREF="../index-2.html#contact"><B>REPORT BUGS OR ERRORS IN THIS DOCUMENT</B></A></H2>
